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Adam_a

WDC Announces Four-Bits-Per-Cell 3D NAND Technology

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Western Digital has a long track record of industry firsts surrounding flash technology, going back nearly 30 years. These first include multi-level cell (MLC) flash technologies using two bits (X2) and three bits (X3) per cell. Utilizing the company’s deep vertical integration capabilities (including silicon wafer processing, device engineering to provide sixteen distinct data levels in every storage node, and system expertise for overall flash management) the company was able to bring this new X4 technology to market. The new BiCS3 X4 technology is stated to deliver storage capacity of 768 gigabits on a single chip, a 50% increase from the prior 512 gigabit chip that was enabled with the three bits per cell (X3) architecture. This increase in capacity will still be able to deliver performance comparable to the BiCS3 X3 technology, according to WD.

 

WDC Announces Four-Bits-Per-Cell 3D NAND Technology

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16 levels of analog voltage per cell. It better have amazing error check and correction. I won't be the first one to try this.

Side note, between higher bits-per-cell and 3D layouts, the bits-per-chip has gone up dramatically. I was expecting SSD prices to decline dramatically as density goes up. But they've stayed about the same (or even increased slightly) over the past year. What gives? The manufacturers can't all be in a conspiracy to prop up prices, can they?

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The demand is outstripping supply at the moment...well, really for the last 18 months or so. All the suppliers and buyers are saying the same thing. There's just not enough NAND production to go around. These die changes are critical to being able to hit the capacity targets the market expects. 

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