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Micron Rebrands XPoint As QuantX & Releases Performance Numbers

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Micron compared their QuantX to a current NVMe SSD. The NVMe SSD hit a write latency of less than 200μs and a read latency of less than 100μs. The QuantX was able to hit write latency of less than 20μs and a read latency of less than 10μs. Comparing a NVMe SSD to QuantX in a U.2 form factor, this time in 4k random 70% read 30% write tests, the QuantX drive in capacities that ranged from 200GB to 1.6TB were all able to hit over 900K IOPS while the 1.6TB NVMe SSD hit just over 200K IOPS. Running the same test this time using HHHL form factor gave similar results for the NVMe SSD while the QuantX, again in all capacities, hit over 1.8 million IOPS.


Micron Rebrands XPoint As QuantX & Releases Performance Numbers

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8 hours ago, Brian said:

So much for 1000x but still should be fun once it gets to market. 

Well, we can settle, so to speak. This image is impressive:

QD1 Performance of 3D XPoint

I guess the real world performance was never going to be as good as advertised - 1000x. It's not a replacement for DRAM for sure.


I wonder how many P/E cycles 3D XPoint/Quant X can take? Especially compared to an MLC 3D NAND SSD at 40nm today? It's advertised to be a lot better than  NAND, but Micron only advertises 25 DWPD.,news-53632.html


Micron also revealed that its first QuantX SSDs would feature 25 DWPD (Drive Writes Per Day) of endurance over a five year period with the first generation of 3D XPoint. In comparison, some enterprise SSDs based on MLC NAND provide up to 10 DWPD, whereas TLC NAND SSDs provide between <1 to 5 DWPD of endurance.


I'm surprised at that one. A 40nm MLC 3D NAND SSD with 28% overprovisioning can do 10 DWPD. A hypothetical 40 nm SLC 3D NAND with 28% overprovisioning could probably do 25 DWPD easily. The real question is, what is the real world endurance of 3D XPoint or is the 25 DWPD just ultra conservative?

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If we borrow a metaphor from radio broadcasting,

then a quad-core 64-bit CPU running at 4 GHz

can generate huge amounts of binary data.

At the other end of the storage path,

we find that 3D XPoint quickly saturates both a PCIe 3.0 x4 link

and a PCIe 3.0 x8 link (note the linear scaling from x4 to x8):




It's the chipset in-between both that is the new bottleneck.



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Micron did write us to say they still expect 1000x by the time it's done. Hard to imagine that will be the case, but we can hope!

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Merely extrapolating now:

900 at PCIe 3.0 x4 link (measured)

1800 at PCIe 3.0 x8 link (measured)

then ...

3600 at PCIe 3.0 x16 link (projected)

7200 at PCie 4.0 x16 link (projected)

assuming perfect scaling.

What would be a better assumption in place of perfect scaling?

My BEST GUESS is that Intel are aiming for PCIe 4.0's 16G clock.

They can leave a future DMI 4.0 link at x4 lanes, and

point high-performance users to x16 PCIe 4.0 expansion slots.

Another admittedly less simple option is to support heterogeneous DRAM banks

e.g. dedicate one of the 3 banks in Intel's triple-channel LGA1366 concept

to Optane, and operate the other 2 banks as quad-channel:

4 DIMM slots in each of those 2 banks,

each of those 2 banks operates in dual-channel mode.


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