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CI Express 3.0 SPECIFICATION finalized

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Hmm, seems like a fairly important announcement on Nov .17th, covered on cdrinfo no less. When will shipping products be announced?

Q3: How does the PCIe 3.0 8GT/s “double” the PCIe 2.0 5GT/s bit rate?

A3: The PCIe 2.0 bit rate is specified at 5GT/s, but with the 20 percent performance overhead of the 8b/10b encoding scheme, the delivered bandwidth is actually 4Gb/s. PCIe 3.0 removes the requirement for 8b/10b encoding and uses a more efficient 128b/130b encoding scheme instead. By removing this overhead, the interconnect bandwidth can be doubled to 8Gb/s with the implementation of the PCIe 3.0 specification. This bandwidth is the same as an interconnect running at 10GT/s with the 8b/10b encoding overhead. In this way, the PCIe 3.0 specifications deliver the same effective bandwidth, but without the prohibitive penalties associated with 10GT/s signaling, such as PHY design complexity and increased silicon die size and power. The following table summarizes the bit rate and approximate bandwidths for the various generations of the PCIe architecture:

PCIe Architecture Raw Bit Rate Interconnect Bandwidth Bandwidth Lane Direction Total Bandwidth for x16 Link

PCIe 1.x 2.5GT/s 2Gb/s ~250MB/s ~8GB/s

PCIe 2.0 5.0GT/s 4Gb/s ~500MB/s ~16GB/s

PCIe 3.0 8.0GT/s 8Gb/s ~1GB/s ~32GB/s

Total bandwidth represents the aggregate interconnect bandwidth in both directions.

PCIe 3.0 specification doubles bandwidth over previous generations

PCI-SIG (, the organization responsible for the widely adopted PCI Express (; PCIe) industry-standard input/output (I/O) technology, announced the availability of the PCIe Base 3.0 specification to its members. The PCIe 3.0 architecture is a low-cost, high-performance I/O technology that includes a new 128b/130b encoding scheme and a data rate of 8 gigatransfers per second (GT/sec), doubling the interconnect bandwidth over the PCIe 2.0 specification. PCIe 3.0 technology also maintains backward compatibility with previous PCIe architectures and provides the optimum design point for high-volume platform I/O implementations across a wide range of topologies. Possible topologies include servers, workstations, desktop and mobile personal computers, embedded systems, peripheral devices and more.

For backwards compatibility, 8b/10b encoding must be supported...though I don't see any reason why a manufacturer would not include that.

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