TheR

MB performance with 4 DIMMS vs 2 DIMMS

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Years back I remember there was quite performance penalty when going from 2 DIMMS to 4 DIMMS RAM configuraction.

I don't remember why was it so, but is this still a case with moderen chipsets and DDR2 memory.

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TheR

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No, this is not a problem with DDR2 or recent DDR memory controllers.

Once upon a time, there was a problem with some specific AMD chipsets where it only officially supported 4 DIMMs at DDR333, when DDR400 was the norm. That got fixed around the time they first officially supported DDR400. Around the same time frame, there were issues around needing to loosen the memory timings when running 4 DIMMs, and only the best motherboards could run 4 modules at the same timings as 2 modules. I think it was usual to have to drop from 1T command rate to 2T, and that could have a 10% impact on memory benchmarks. Oh, and it made a difference whether you were using single sided or double sided DIMMs - the larger modules were double sided, and had more of these problems.

Anyway, I don't think that's been a problem on any chipset produced in the last 3 or 4 years, including all the DDR2 ones and (IIRC) all the AMD64 ones as well. This was an Athlon XP era problem.

Edited by Spod

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I vaguely remember there was a big thing on Anand's where 4 DIMM's turned out to be slower than 1. Later on it was discovered that the benchmark software/config itself was the cause of the trouble. Typically servers will benefit from more memory sticks, desktop systems usually won't benefit a lot from it. That's why I bought 2 2 GB sticks rather than 4 1 GB sticks for my new machine - leaves me with 2 banks for an upgrade to 8 GB.

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This is not the fault of anyone's memory controller, rather it is the laws of physics at work and the boundaries of the JEDEC specs.

For plain unbuffered DDR(1), DDR400 is electrically calculated for one DIMM per channel, two at DDR333, etc. Sometimes you could make two DIMMs work at DDR400 in the same channel, but at a command rate of 2T, a rather insignificant performance penalty.

Later AMD64 iterations supplied a tweaked DDR(1) memory controller to pacify the whiners, but this as I mentioned is out of JEDEC's original spec. Not sure what DDR2's specs are like in this regard. Servers make out okay with multiple DIMMs per channel because they use registered RAM which reduces the electrical load, presenting two address lines rather than the typical 16-18 for unbuffered DIMMs.

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This is not the fault of anyone's memory controller, rather it is the laws of physics at work and the boundaries of the JEDEC specs.

For plain unbuffered DDR(1), DDR400 is electrically calculated for one DIMM per channel, two at DDR333, etc. Sometimes you could make two DIMMs work at DDR400 in the same channel, but at a command rate of 2T, a rather insignificant performance penalty.

Later AMD64 iterations supplied a tweaked DDR(1) memory controller to pacify the whiners, but this as I mentioned is out of JEDEC's original spec. Not sure what DDR2's specs are like in this regard. Servers make out okay with multiple DIMMs per channel because they use registered RAM which reduces the electrical load, presenting two address lines rather than the typical 16-18 for unbuffered DIMMs.

The Asus A8N5X board seems to run 2 1gig sticks fine at ddr400 put it 4 1 gig sticks and it reverts tp ddr333.I guess that's the Jedec spec.In reality though for general purpose computing is much lost here in terms of system speed.

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