The most common current Xeons, the XeonDP (almost always just called Xeon) is the one used in dual processing environments and comes in a 603 pin package for 400FSB up to 3GHz and a 604 pin package for 533FSB up to 3.06GHz. They all have 512KB of L2 cache except the new (ish) 1MB job, and are based on the Prestonia core. The Prestonia core is functionally all but identical to P4 Northwood.
As for the extra pins, Intel datasheets show damn near all of them as being Vcc or ground, as someone else has stated. This is, supposedly, for "extra stability" for the markets Xeon is aimed at.
The Gallatin core is used in XeonMP which supports up to 4 way (8 way??) configurations and also has 512K of L2 cache, but comes with either 2MB of 1MB of L3 cache. The Gallatin has also been called to the front to see service as the P4 Extremely Desperate Edition.
I belive all of the above to be correct, please feel free to correct me if you know better. Basically, the answer to the question is that the differences are largely artificial and are to extract more cash from people buying SMP. Besides the SMP support and the sockets the P4 and Xeon are identical. It's all a big rip off.