Let me second Brad.B on this one. The reason a faster DRAM doesn't translate linearly into performance is simple - not all memory-accessing instructions actually go all the way to DRAM. That may sound nonsensical, yes, but the reason is simple: caches. Most loads and stores actually get resolved into the L1 and L2 cache (a Core 2 Duo has about 4MB of L2 cache ... that can accomodate most applications' working set quite easily).
BTW, a load that hits into L1 has a latency of about 4-5 cycles. If it misses into the L1, but hits in the L2, the latency is around 10->20 cycles. Finally, if it misses all the way to memory (i.e., DRAM), the latency is around 200->400 cycles (!!!).