Quote
The PCI bus was moved from the northbridge to the southbridge, and thus the ATA controllers no longer have to share PCI bus bandwidth.
You mean the PCI bus is moved from the southbridge to the northbridge, right? (not the other way round)
True, if you use a separate hub link / v link to connect each PCI-X bus to the northbridge, then the IDE controller connected to the PCI-X bus is just a counterpart to the southbridge; they all talk directly to the northbridge via their own hub link. But right now this architecture is only found in server chipsets like the Intel E7500 chipset for the Xeon. I don't think we'll see a desktop chipset with this architecture for quite a while.
For the upcoming Springdale chipset (Q2 2003), we'll see the SATA controller built into the southbridge (ICH5), like what Jan said. Not as good as a separate hub link for the controller but at least now the controller will have access to the bandwidth of the NB-SB interconnect and not be restricted by the bandwidth of the PCI bus. At this point, SATA RAID will be faster than PATA RAID but only because no one is making a PATA RAID controller integrated into the southbridge.