[Brian]

Intel and Micron have announced the delivery of 3-bit-per-cell (3bpc) NAND flash built on 25nm process technology. Samples are going out and full line production is expected this year.

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[Brian]

I do wonder what the performance and longevity hits might be here. With TLC the controller and other components have to do more work and the impact on the NAND will be higher. Should be interesting though..

[udaman]

Brian, on 17 August 2010 - 12:54 PM, said:

I do wonder what the performance and longevity hits might be here. With TLC the controller and other components have to do more work and the impact on the NAND will be higher. Should be interesting though..

Non-sequitur? or do you have a link to a white paper article on TCL tech that supports that contention?

Is there a link(s) to this announcement by either Intel or Micron?

I still recall Samsung's 2006 "announcement" of 40nm 'charged trap' NAND tech, which was likewise said to be sampling and full production later in the year/and or shortly, lol. Turned out to be classic vaporware.

I guess Intel/Micron have to announce something, otherwise Samsung/Toshiba juggernaut take over the spotlight.

I note that mention of "8GB" TLC chips. Given that the 'announced' Toshiba 32nm DDR Toggle mode NAND's will/are supposedly coming in packages of 8GB, 16GB & 32GB...you have to wonder why the 25nm process Intel/Micro chips have unimpressive capacity?

http://www.toshiba.c...&lineid=1735086

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Toshiba offers a lineup of 32nm DDR Toggle Mode NAND, in MLC versions with densities of 64Gb, 128Gb and 256Gb and SLC versions with densities of 32Gb, 64Gb and 128Gb

[Brian]

The only thing clipped from the press release are the two quotes about how great Intel and Micron NAND is

I'll try to find something to quote on the processor usage of TLC, but I've heard the comment more than once from people we talk to in the business.

[udaman]

http://www.electroni...sh.ready.to.go/

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Unnamed customers should already have samples of the new memory today. Production devices with the improved storage should be available before the end of the year. The technology isn't expected to have a direct effect on Intel's solid-state drive roadmap, which will still need faster but lower density memory to produce 600GB SSDs in the same period.

as typical, electronista doesn't supply a link for their contention...where did they get this info?

Wonder *which* "next gen" tech flash will need advanced error correction, and doesn't that also apply to DRAM also?

http://www.electroni...tic.processing/

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The technology is reportedly capable of decoding real-world flash data with error rates as high as 1 bit per 100. Such performance is expected to be necessary for next-generation flash, as increasing storage density brings higher error rates. Beyond <20nm process???

Lyric plans on beginning mass production sometime in the next 12 months. [via Wired]

[[ETA]MrSpadge]

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With TLC the controller and other components have to do more work

In TLCs there are 4 possible states opposed to 3 in 2-bit MLCs. Retrieving your actual information thus requires more processing (=transistors) at the gate level. It's only neccessary once for the entire chip, so surely a tradeoff well worth it.

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I still recall Samsung's 2006 "announcement" of 40nm 'charged trap' NAND tech

Kind of funny if you consider that every flash device is a potential well (=trap) for electrons (=charges). And if you trap charges in the trap it's probably fair to say you've got a charged trap

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I note that mention of "8GB" TLC chips. Given that the 'announced' Toshiba 32nm DDR Toggle mode NAND's will/are supposedly coming in packages of 8GB, 16GB & 32GB...you have to wonder why the 25nm process Intel/Micro chips have unimpressive capacity?

1. The article talks about the 8 GB 25 nm TLC chip. It does not say that other sizes won't be made.
2. Another answer can be found right in your question, marked in bold. Many chips can comprise a package.

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The technology isn't expected to have a direct effect on Intel's solid-state drive roadmap, which will still need faster but lower density memory to produce 600GB SSDs in the same period.

I read this as "we're not using it for the next gen of SSDs, as the performance and reliability of TLC is not there or not proven yet".

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Wonder *which* "next gen" tech flash will need advanced error correction, and doesn't that also apply to DRAM also?

They'll all have to handle increased error rates. How much for which tech / manufacturer and how much will be offset by speed compromises I can't tell.

Regarding DRAM: it's also storage, but fundamentally very different. The longevity of flash suffers because (comparably) large currents have to flow every time a cell is written. These currents are needed so that a few electrons tunnel through the gate oxide and are trapped. DRAM doesn't have any such mechanism. BTW: writes are slow for flash because you need to wait for quite some time until a few electrons have eventually tunneled. Again, not for DRAM.
The other problem is that, as your gate becomes smaller, less electrons are used to store the information. Therefore loosing a few becomes ever more devastating, up to the point where the information is lost. DRAM stores the information in small capacitors, which is totally different. More charges are used and the capacitors loose them so quickly anyway that they're refreshed every few 10 ns. Shrinking the capacitors is certainly not trivial as well, but is not related to the problems flash faces upon scaling.

MrS